ADS5263IRGCT-NM

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com

1. Describe

The ADS5263IRGCT-NM has a 14-bit low power mode in which it operates as a quad 14-bit ADC. Compared with the 16-bit mode, the 16-bit front-end stage is powered down, and some power consumption is almost halved. The 14-bit mode supports a 2-Vpp full-scale input signal with a typical SNR of 74-dBFS. The ADS5263 can dynamically switch between the two resolution modes. This allows the system to use the same parts in high-resolution, high-power mode or low-resolution, low-power mode. The device also features a digital processing block that integrates several common digital functions such as digital gain. It includes a digital filter block with built-in decimation filter. The decimation rate is also programmable. This makes it suitable for narrowband applications where filters can be used to improve SNR and remove harmonics while reducing the output data rate. The device includes an averaging mode that averages both channels to improve SNR. A very unique feature is the programmable mapper block, which allows flexible mapping between input channels and LVDS output pins. This helps to greatly reduce the complexity of the LVDS output routing and potentially reduces the cost of the system board by reducing the number of PCB layers. Device specifications are over the industrial temperature range of –40°C to 85°C.

2. Feature

    1. Maximum sample rate: 100 MSPS

    2. Programmable device resolution

        – Quad channel, 16-bit, high SNR mode

        – Quad-channel, 14-bit, low-power mode

    3. 16-bit high SNR mode

        – 1.4 W total power at 100 MSPS

        – 4 Vpp full scale input

        – 85-dBFS SNR, fin = 3 MHz, 100 MSPS

    4. 14-bit low power mode

        – 785 mW total power at 100 MSPS

        – 2-Vpp full-scale input

        – 74-dBFS SNR, fin = 10 MHz

        – Integrated fixture (for connecting the CCD sensor)

    5. Low frequency noise suppression

    6. Digital processing module  

        – Programmable FIR decimation filter

        – Programmable digital gain: 0 dB to 12 dB

        – 2 or 4 channel averaging

    7. Programmable mapping between ADC inputs Channel and LVDS output pins - simplifying the board design

    8. Multiple test modes to verify FPGA/receiver data acquisition

    9. Serial LVDS output

  10. Internal and external references

  11. 3.3V analog supply

  12. 1.8V digital power

  13. Recovery from 6-dB overload within 1 clock cycle

  14. box:

        – 9mm × 9mm 64-pin QFN

        – Non-magnetic packaging options for MRI systems

  15. CMOS technology

3. Application

    1. Medical Imaging - MRI

    2. Spectroscopy

    3. CCD imaging

4. Pin configuration

5. Application Information

The ADS5263 is a high performance 16-bit quad-channel ADC with sampling rates up to 100 MSPS. The conversion process is initiated by the rising edge of the external input clock, the analog input signal is sampling. The sampled signal is sequentially converted by a series of small resolution stages, and the output Incorporated in a digital correction logic block. On every clock edge, the sample is propagated through the pipe, This results in a data delay of 16 clock cycles. The output is available as 16-bit data in serial LVDS format, encoded In offset binary or binary 2s complement format. The device also has a 14-bit low power mode and can operate as a quad 14-bit ADC. With the 16-bit front-end stage powered down, the device consumes almost half the power compared to 16-bit mode. This The ADS5263 can dynamically switch between the two resolution modes. This allows the system to use the same Some are in high-resolution, high-power mode or low-resolution, low-power mode. The INxA pins are used as 16-bit ADC inputs and the INxB pins are used as 14-bit ADC inputs.