DS92LV1023TMSAX

Interface - Serializers, Deserializers

DS92LV1023TMSAX is a quad 10-bit Serializer/Deserializer device that leverages the 2.5V, 3.3V Low Voltage Differential Signaling (LVDS) interface standard. This device provides four LVDS transmitter outputs and four LVDS receiver inputs, and is intended for non-critical real-time applications, like Digital Video Interface (DVI).

Application Field

The DS92LV1023TMSAX is suitable for a variety of data link applications where high data rates, low power, and low emissions are required. Its small size, low power requirements, near zero electromagnetic interference (EMI), low cost, and all-CMOS construction make this product particularly attractive for use in mobile and handheld applications. This product is ideal for applications such as interfaces between LVDS chips, LCD data link applications, and interface with novel physical layer components such as high speed ADCs. With the increased data rate over the LVDS interface, the DS22LV1023TMSAX is a good choice for links in displays operating at resolutions up to UXGA (1600 x 1200).

Working principle

The DS92LV1023TMSAX is a Serializer/Deserializer (SerDes) device designed to provide a single-port of LVDS for both transmit and receive operations. A separate LVDS (differential) data signal and a reference clock are used for the transmit and receive functions. The serial data is parallelized and synchronized to the reference clock on the receive side and serialized on the transmit side. The LVDS transceivers on the outputs of the DS92LV1023TMSAX are capable of providing an output data rate of up to 900 Mbps. In order to improve signal integrity and to reduce jitter, the transmit port has a built-in internal clock delay of up to 4 bit periods.

The 10-bit output of the serializer is configured as four lanes. The clock output of the serializer can be phase-shifted in steps of 0.25 UI as necessary. The phase-shift can be programmed either to be used as a transmit clock phase-shift once placed on the FIFO or as a clock phase shift while outputting the data (pre-shifting). The transmit clock is recovered from the transmitted data. The recovered clock has an internal phase-shift setting and an output phase-shift setting. The phase jitter on the output of the DS92LV1023TMSAX can be set to 0.1 UI.

The DS92LV1023TMSAX deserializer operates in a similar way to the serializer, except it provides a 10-bit parallel output. The deserializer uses two LVDS reference clocks in order to ensure proper data alignment. One clock is used for the deserializer clock, while the other clock is used to read the data from the LVDS communication link. In addition, the deserializer also features an internal phase-shifter that can be adjusted to enhance signal integrity.

The DS92LV1023TMSAX is a high-performance device that enables LVDS communication links to be interfaced between multiple ICs with data rates up to 900 Mbps. This device provides four LVDS transceivers for both transmit and receive operations, and is intended for non-critical real-time applications. With its small size, low power requirements, near zero EMI, low cost, and all-CMOS construction, it is a good choice for mobile and handheld applications.