MT52L256M32D1PF-107 WT:B

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1. Description

Mobile LPDDR3 is a high-speed SDRAM internally configured as 8 banks of memory devices. LPDDR3 uses a double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus is used to transfer command, address and bank information. Each command uses one clock cycle, during which information is transferred on the rising and falling edges of the clock. LPDDR3 uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per DQ per clock cycle on the I/O pins. A single read or write access to LPDDR3 actually consists of a single 8n-bit wide, one-clock-cycle data transfer in the internal SDRAM core and eight corresponding n-bit-wide, half-clock-cycle data transfers in the I/O pins foot. 

2. Features

    1. Ultra-low-voltage core and I/O power supplies

    2. Frequency range

        – 1066–10 MHz (data rate range: 2133–20 Mb/s/pin)

    3. 8n prefetch DDR architecture

    4. 8 internal banks for concurrent operation

    5. Multiplexed, double data rate, command/address inputs; commands entered on each CK_t/CK_c edge

    6. Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c)

    7. Programmable READ and WRITE latencies (RL/WL)

    8. Burst length: 8

    9. Per-bank refresh for concurrent operation

  10. Temperature-compensated self refresh (TCSR)

  11. Partial-array self refresh (PASR)

  12. Deep power-down mode (DPD)

  13. Selectable output drive strength (DS)

  14. Clock-stop capability

  15. On-die termination (ODT)

  16. RoHS-compliant, “green” packaging

3. Options

    1. VDD1/VDD2/VDDCA/VDDQ: 1.8V/1.2V/1.2V/1.2V

    2. Array configuration

        – 256 Meg x 32 (SDP)

        – 512 Meg x 32 (DDP)

        – 1 Gig x 32 (QDP)

    3. Device configuration

        – 1 die in package

        – 2 die in package

        – 4 die in package

    4. 178-ball FBGA “green” package

        – 11mm x 11.5mm x 0.85mm MAX,1 die, 2 die

        – 12mm x 11.5mm x 1.0mm MAX, 4 die

    5. Speed grade, cycle time

        – 938ps @ RL = 16

        – 1.071ns @ RL = 14

    6. Operating temperature range

        – From –30°C to +85°C