SP708EN-L

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The SP708EN-L is a member of the SP700 series of supervisory IC’s developed by Silicon Laboratories, specifically designed for embedded applications. The IC features an integrated manual reset, watchdog timer, and logic output, saving the time and effort of having to develop and implement an additional reset IC. The reset logic operates independent of the power supply voltage, making the IC suitable for applications with multiple power supplies.

Functionality

At the core of the IC is its reset function, which is triggered by several events. The primary reset events are triggered by manual reset input or by undervoltage detector circuitry that can be programmed for a specific voltage level, usually 3.3V. A secondary event is triggered when the watchdog timer times-out and a logic output pin is triggered. To prevent the reset from resetting after a power off and then on, the reset is latched in the reset state until the manual reset input is pulled low.

The watchdog timer consists of a 14-bit periodic down counter which counts down to 0 every 128ms. Once it reaches 0 it triggers a reset if the watchdog enable pin is high. When the clock input is driven by a 3V signal, the IC can sample the watchdog enable pin with 8 millisecond accuracy. The timer can be refreshed by driving the clock input low or by being disabled.

The logic output pin is triggered when a reset is activated, which can be used drive external logic or to reset another IC. The logic output is active low and is pulled low when a reset is triggered, remaining low until the manual reset is pulled low. It is equipped with an output push-pull driver to ensure sufficient current is supplied on the output pin, but can be disabled when the reset occurs.

Applications

The primary application of the SP708EN-L is in embedded systems and microcontrollers. Its reset logic is especially useful in applications where there is a need to distinguish between power-down and power-up situations, such as in power management systems. Its ability to provide logic output and reset logic independent of the power supply makes it ideal for systems where multiple power supplies are present. It can also be used as a watchdog timer for applications that require a periodic check on system status.

Working Principle

The SP708EN-L’s reset logic operates by detecting an undervoltage condition on the Vcc pin, which is followed by either a manual reset or a triggered watchdog timer reset. If a reset is triggered, the IC will latch and drive the output pin low for an active low reset. If the manual reset pin is high, the reset is cleared and the output is driven high. If the watchdog timer is enabled, and the timer reaches the timeout threshold of 128ms, the reset is triggered and the logic output is driven low until the manual reset is pulled low.

The SP708EN-L also has a number of configuration options available. It can be configured to detect either rising or falling edges on the reset input, and the default timeout is 128ms but can be programmed to any value between 128ms and 8193ms. The undervoltage protection can also be configured; the default threshold is 3.3V but can be programmed to any value between 0.8V and 4.3V. The logic output can be disabled when a reset is triggered, and the watchdog timer can be disabled, enabled, or configured for continuous reset.

Conclusion

The SP708EN-L is a versatile supervisory IC perfect for embedded applications. Its reset logic is independent of the power supply and can detect a wide range of voltages. The watchdog timer feature provides an effective way to periodically check system status, while the logic output pin can be used as a reset signal for external logic or ICs. It is ideal for applications where multiple power supplies are present or for power management systems, as it can distinguish between power on and power off situations, providing reliable system monitoring.

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