TM4C123GH6PMTR

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1. Describe

Texas Instruments (TI) Tiva™ C Series microcontrollers provide designers with a high-performance ARM® Cortex™-M-based architecture with broad integration capabilities and a robust ecosystem of software and development tools. Targeting performance and flexibility, the Tiva™ C-Series architecture offers an 80 MHz Cortex-M with an FPU, various integrated memories, and multiple programmable GPIOs. Tiva™ C Series devices provide consumers with a tool to minimize board cost and design cycle time in a cost-effective solution by integrating application-specific peripherals and providing a comprehensive software library. Tiva™ C-Series microcontrollers provide faster time-to-market and cost savings, and are the first choice for high-performance 32-bit applications. For applications requiring extreme power savings, the TM4C123GH6PM microcontroller features a battery-backed hibernate module that effectively powers down the TM4C123GH6PM to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, real-time counter (RTC), multiple wake-up from sleep options, and dedicated battery-backed memory, the sleep module makes the TM4C123GH6PM microcontroller ideal for battery applications. In addition, the TM4C123GH6PM microcontroller benefits from ARM's widely available development tools, system-on-chip (SoC) infrastructure IP applications, and a large user community. In addition, microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements, thereby reducing cost. Finally, most of the TM4C123GH6PM microcontroller code is compatible with the Tiva™ C series product line, providing flexibility across designs. Texas Instruments (TI) offers a complete solution to get to market quickly with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a robust network of support, sales, and distributors.

2. Feature

    1. 32-bit ARM Cortex-M4F architecture optimized for small form factor embedded applications

    2. 80-MHz operation; 100 DMIPS performance

    3. Excellent processing performance combined with fast interrupt handling

    4. Thumb-2 mixed 16-bit/32-bit instruction set provides the high performance expected from 32-bit ARM cores in the compact memory size typically associated with 8- and 16-bit devices, typically in the range of a few kilobytes for microcontrollers memory for device-level applications

         – Single cycle multiply instruction and hardware divide

         – Atomic bit manipulation (bit banding) for maximum memory utilization and simplified peripheral control

         – Unaligned data access, allowing data to be efficiently packed into memory

    5. IEEE754-compliant single-precision floating-point unit (FPU)

    6. 16-bit SIMD vector processing unit

    7. Fast code execution allows slower processor clocks or increased sleep mode time

    8. Harvard architecture is characterized by separate instruction and data busses

    9. Efficient processor cores, system and memory

  10. Hardware divide and multiply-accumulate for fast digital signal processing

  11. Saturation algorithm for signal processing

  12. Deterministic, high-performance interrupt handling for time-critical applications

  13. Memory Protection Unit (MPU) provides privileged mode for protected operating system functions

  14. Enhanced system debugging with extensive breakpoint and trace capabilities

  15. Serial wire debug and serial wire trace reduce the number of pins required for debug and trace

3. Application

    1. Low-power, handheld smart devices

    2. Gaming equipment

    3. Home and commercial site monitoring

    4. Motion Control

    5. Medical equipment

    6. Test and measurement equipment

    7. Factory Automation

    8. Fire Safety

    9. Smart Energy/Smart Grid Solutions

  10. Intelligent lighting control

  11. Transportation

4. Function Description

The JTAG module consists of a Test Access Port (TAP) controller and a serial shift chain Update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the rising edge of TCK, the sequence of values captured on TMS. The TAP controller determines when the serial shift chain captures new data, transfers the data from TDI to TDO, and updates the parallel load registers. The current state The TAP controller also determines whether the instruction register (IR) chain or one of the data registers (DR) chain is being accessed. A serial shift chain with parallel load registers consists of a single instruction register (IR) chain and multiple data register (DR) chains. The current instruction register loaded in a parallel load determines which DR chain tap controller is captured, shifted, or updated during sequencing. Some instructions, such as EXTEST, operate on data currently in the DR chain and do not capture, transfer, or update any chain. plugin tructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected .