MT47H128M8SH-25E IT:M

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1. Describe

DDR2 SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data words per clock cycle on the I/O ball. A single read or write operation to DDR2 SDRAM actually involves a single 4n-bit wide, two-clock-cycle data transfer to the internal DRAM core and four corresponding n-bit-wide, half-clock-cycle data transfer I/O balls. Bidirectional data strobes (DQS, DQS#) are transmitted externally with the data for data capture by the receiver. DQS is a strobe signal transmitted by DDR2 SDRAM during READ and memory controller during WRITE. DQS is edge-aligned with READ data and center-aligned with WRITE data. The x16 products have two data strobes, one for the low byte (LDQS, LDQS#) and one for the high byte (UDQS, UDQS#). DDR2 SDRAM operates on differential clocks (CK and CK#); the intersection of CK going high and CK# going low is called the rising edge of CK. Commands (address and control signals) are registered on every rising edge of CK. Input data is registered on both edges of DQS and output data is referenced to both edges of DQS and both edges of CK. Read and write accesses to DDR2 SDRAM are burst-oriented; accesses begin at a selected location and continue for the programmed number of locations in the programmed order. Access begins with the registration of an ACTIVATE command, followed by a READ or WRITE command. The address bits registered with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered with the READ or WRITE command are used to select Bank and starting column location for burst access. DDR2 SDRAM offers programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports eight burst reads interrupted by another read or eight burst writes interrupted by another write. The auto-precharge feature can be enabled to provide a self-timed row precharge that starts at the end of a burst access. Like standard DDR SDRAM, DDR2 SDRAM's pipelined, multi-bank architecture supports concurrent operation, providing high effective bandwidth by hiding row precharge and activation times. Provide self-refresh mode and power saving, power down mode. All inputs are compliant with the JEDEC standard for SSTL_18. All full drive strength outputs are SSTL_18 compatible.

2. Features

    1. VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V

    2. JEDEC-standard 1.8V I/O (SSTL_18-compatible)

    3. Differential data strobe (DQS, DQS#) option

    4. 4n-bit prefetch architecture

    5. Duplicate output strobe (RDQS) option for x8

    6. DLL to align DQ and DQS transitions with CK

    7. 8 internal banks for concurrent operation

    8. Programmable CAS latency (CL)

    9. Posted CAS additive latency (AL)

  10. WRITE latency = READ latency - 1 t CK

  11. Programmable burst lengths: 4 or 8

  12. Adjustable data-output drive strength

  13. 64ms, 8192-cycle refresh

  14. On-die termination (ODT)

  15. Industrial temperature (IT) option

  16. RoHS-compliant

  17. Supports JEDEC clock jitter specification