| Allicdata Part #: | CY7C1361C-133AXC-ND |
| Manufacturer Part#: |
CY7C1361C-133AXC |
| Price: | $ 8.78 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | Cypress Semiconductor Corp |
| Short Description: | IC SRAM 9M PARALLEL 100TQFP |
| More Detail: | SRAM - Synchronous Memory IC 9Mb (256K x 36) Paral... |
| DataSheet: | CY7C1361C-133AXC Datasheet/PDF |
| Quantity: | 35 |
| 1 +: | $ 7.97580 |
| 10 +: | $ 7.38801 |
| 25 +: | $ 7.22078 |
| 72 +: | $ 7.18109 |
| 144 +: | $ 6.32199 |
| 288 +: | $ 6.00922 |
| 504 +: | $ 5.94755 |
| 1008 +: | $ 5.74929 |
| Write Cycle Time - Word, Page: | -- |
| Base Part Number: | CY7C1361 |
| Supplier Device Package: | 100-TQFP (14x20) |
| Package / Case: | 100-LQFP |
| Mounting Type: | Surface Mount |
| Operating Temperature: | 0°C ~ 70°C (TA) |
| Voltage - Supply: | 3.135 V ~ 3.6 V |
| Memory Interface: | Parallel |
| Access Time: | 6.5ns |
| Series: | -- |
| Clock Frequency: | 133MHz |
| Memory Size: | 9Mb (256K x 36) |
| Technology: | SRAM - Synchronous |
| Memory Format: | SRAM |
| Memory Type: | Volatile |
| Part Status: | Active |
| Packaging: | Tray |
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CY7C1361C-133AXC is an asynchronous monolithic static random-access memory (SRAM). It is made up of 1,048,576 (1Mb) bits of CMOS integrated circuits (ICs), with the data input and output pins connected in 8-bit wide parallel ports. It features a maximum operating frequency of 35MHz, with a maximum power supply current of 5mA and a standby current of 25µA.
The application field of CY7C1361C-133AXC involves image data storage, bus interface memory, normal operation memory in data-processing systems, and ultra-high speed data transfer. It can be used as EDO DRAM, or Fast-page mode DRAM to achieve high performance, or as zero-wait-state SRAM for low power designs.
The working principle of the CY7C1361C-133AXC is a combination of clocking, write/read/decode, and dynamic circuitry. When data is written to or read from the device, it is clocked onto the internal circuitry, where it undergoes a series of write/read/decode processes, depending on the type of memory operation. This results in data being written to or read from the storage cells. The device is capable of writing and reading data at a high speed with no external refresh circuitry required.
The CY7C1361C-133AXC integrates dynamic circuitry that allows high-speed operation and no external refresh circuitry. It also has a number of other features, such as bidirectional data transfers, chip enable and output enable to allow interface with different memory interfaces, such as microprocessors, DMA controllers, emulators, etc., and two power supply pins for a single or dual voltage operation.
CY7C1361C-133AXC provides the flexibility, speed and density needed for a wide variety of applications. Its combination of advanced features is ideal for applications requiring high-speed access and low-power operation. Its design is optimized for maximum performance in applications that require low-power operation and high-speed write/read operations, such as image registration and image data storage. Additionally, its fast-page mode operation makes it perfect for applications such as bus interface memory, where data needs to be transferred quickly.
The specific data is subject to PDF, and the above content is for reference
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CY7C1361C-133AXC Datasheet/PDF