S34MS02G200BHI000

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1. Describe

The SkyHigh S34MS01G2, S34MS02G2 and S34MS04G2 series operate from 1.8 VCC and VCCQ power supplies and feature x8 or x16 I/O interfaces. Its NAND cells provide the most cost-effective solution for the solid-state mass storage market. Memory is divided into blocks that can be erased independently, so valid data can be retained while erasing old data. The page size for x8 is (2048 + spare) bytes; for x16 (1024 + spare) words. Each block can be programmed and erased for up to 100,000 cycles with ECC (Error Correcting Code) enabled. In order to prolong the lifetime of NAND flash devices, ECC must be implemented. The chip supports CE# don't care function. This feature allows the microcontroller to download code directly from the NAND flash device, since a CE# transition does not stop the read operation. These devices feature read caching to improve read throughput for large files. During a cache read, the device loads data into cache registers while transferring previous data to the I/O buffer for reading. As with all other 2 kB page NAND flash devices, program operations typically write 2 KB (x8) or 1 kword (x16) in 300 µs, while erase operations typically execute on 128 kB in 3 ms (S34MS01G2) block (x8) or 64-kword block (x16). Furthermore, due to the multi-plane architecture, two pages can be programmed at once (one per plane) or two blocks can be erased at one time (again, one per plane). The multi-plane architecture reduces program time by 40% and erase time by 50%. In multiplane operation, data in a page can be read out with a cycle time of 45 ns per byte. The I/O pins serve as ports for command and address input and data input/output. The interface allows pin count reduction and easy migration to different densities without rearranging the footprint. Commands, data, and addresses are brought in asynchronously using the CE#, WE#, ALE, and CLE control pins. An on-chip program/erase controller automatically performs all read, program and erase functions, including pulse repetition (when required) and internal verification and margining of data. The WP# pin can be used to provide hardware protection for program and erase operations. Output pin R/B# (open-drain buffer) signals device status during each operation. It identifies whether the program/erase/read controller is currently active. Using an open-drain output allows ready/busy pins from multiple memories to be connected to a single pull-up resistor. In systems with multiple memories, the R/B# pins can be tied together to provide a global status signal. The reprogramming feature allows optimized defective block management - when a page programming operation fails, data can be programmed directly into another page within the same array section without the time-consuming serial data insertion stage. Multiplane copy-back is also supported. Allows reading data after Copy Back Read (for single-plane and multi-plane cases). In addition, Cache Program and Multi-Plane Cache Program operations improve program throughput by using cache registers to program data.

2. Feature

    1. Density

        - 1Gb / 2Gb / 4Gb

    2. Architecture

        - I/O bus width: 8 bits/16 bits

    3. NAND flash interface

        - Compatible with Open NAND Flash Interface (ONFI) 1.0

        - Address, data and command multiplexing

    4. Power supply voltage

        - 1.8V device: VCC = 1.7V ~ 1.95V

    5. Security

        - One Time Programmable (OTP) area

        - Serial number (unique ID) (contact factory for support)

        - Disable hardware program/erase during power transition

    6. Additional functions

        - 2 Gb and 4 Gb parts support multiplane program and erase commands

        - Support copy back program

        - 2 Gb and 4 Gb parts support Multiplane Copy Back Program

        - Support read cache

    7. Electronic signature

        - Manufacturer number: 01h

    8. Working temperature

        - Industrial: -40 °C to 85 °C

        - Industrial Plus: -40 °C to 105 °C

3. Performance

    1. Page reading/programming

        - Random access: 25 µs (maximum) (S34MS01G2)

        - Random access: 30 µs (maximum) (S34MS02G2, S34ML04G2)

        - Sequential access: 45 ns (min)

        - Programming time/multiplane programming time: 300 µs (typ.)

    2. Block erase (S34MS01G2)

        - Block Erase Time: 3.0 ms (Typical)

    3. Block erase/multi-plane erase (S34MS02G2, S34MS04G2)

        - Block Erase Time: 3.5 ms (Typical)

    4. Reliability

        - 100,000 Program/Erase Cycles (Typical) (with 4-bit ECC per 528 Bytes (x8) or 264 Words (x16))

        - 10-year data retention (typical)

        - for a planar structure (1-Gb density)

        - For both planar structures (2-Gb and 4-Gb densities)

    5. Package options

        - Lead-free and low-halogen

        - 48-pin TSOP 12 × 20 × 1.2 mm

        - 63 ball BGA 9 × 11 × 1mm

        - 67-Ball BGA 8 × 6.5 × 1 mm (S34MS01G2, S34MS02G2)