JS28F128J3F75A

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1. Describe

This document contains information about the features, operation, and specifications of the Numonyx® embedded flash memory (J3 65 nm) single bit per cell (SBC) device. Unless otherwise stated in the rest of this document, Numonyx® embedded flash memory (J3 65 nm) single bit per cell (SBC) device is called J3 65 nm SBC. The J3 65 nm SBC device provides improved mainstream performance and enhanced safety features, leveraging the high quality and reliability based on NOR 65-nanometer technology. The J3 65 nm SBC device is available in 128 Mbit, 64 Mbit, and 32 Mbit densities, providing reliable low-voltage capability (3 V read, program, and erase) and high-speed, low-power operation. J3 65 nm SBC equipment utilizes proven Manufacturing experience is very suitable for code and data applications that require high density and low cost, such as networking, telecommunications, digital set-top boxes, recording and digital imaging. Numonyx flash memory components also provide a new generation of forward compatible software support. By using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage of the density upgrades and optimized write capabilities of future Numonyx flash memory devices.

2. Features

    1. architecture

        — Symmetrical 128 KB blocks

        — 128 Mbit (128 blocks)

        — 64 Mbit (64 blocks)

        — 32 Mbit (32 blocks)

        — Blank check to verify erased blocks

    2. Performance

        — Initial access speed: 75ns

        — 25 ns 8-word asynchronous page mode read

        — 256 words in x16 mode are written into the buffer, 256 words Byte write buffer in x8 mode; 1.41 µs per byte effective programming time

    3. System voltage

        — VCC = 2.7V to 3.6V

        — VCCQ = 2.7V to 3.6V

    4. Package

        — 56-lead TSOP

        — 64-Ball Easy BGA package

    5. Safety

        — Enhanced code security options protect

        — VPEN = absolute protection of Vss

        — Single block lock

        — Block erase/program lock during power supply transition

        — Password access function

        — One-time programmable register: 64 OTP bits, using unique programming Information provided by Numonyx 64 OTP bits for customers to use Programming

    6. software

        — Program and erase suspend support

        — Numonyx® Flash Data Integrator (FDI)

        — Common Flash Interface (CFI) compatible

        — Scalable command set

    7. Quality and reliability

        — Operating temperature:

             -40 °C to +85 °C

        — 100K minimum erase cycle per block

        — 65nm flash memory technology

        — Comply with JESD47E

3. Functional Overview

The J3 65 nm SBC series contains high-density memory organized in any of the following configurations:

    1. 16-MB or 8-MW (128-Mbit), organized into 128 128-KB erase blocks.

    2. 8-MB or 4-MW (64-Mbit), organized into 64 128-KB erase blocks.

    3. 4-MB or 2-MW (32-Mbit), organized into 32 128-KB erase blocks.

The J3 65 nm SBC device includes new safety features in the 0.13 µm version of the J3 series (previously). These new security features prevent code changes through different protection schemes that can be implemented according to user requirements. J3 65 nm SBC optimized architecture and interface significantly increase reads Improve performance by supporting page mode reads. This read mode is very suitable for non-clocked memory systems. Its Common Flash Interface (CFI) allows software algorithms to be used throughout the process Equipment series. This allows device-independent JEDEC ID and JEDEC ID and Forward and backward compatible software support for designated flash memory devices family. Flash memory suppliers can standardize their existing interfaces for a long time compatibility. Scalable Command Set (SCS) allows a single simple software driver to be used in all hosts The system is suitable for all SCS-compatible flash memory devices and is independent of system-in-package (for example, memory card, SIMM, or direct board placement). return, SCS provides the highest system/device data transfer rate, and minimizes device and System-level implementation costs. Command User Interface (CUI) as the interface between system processors And the internal operation of the equipment. Valid command sequence written to CUI Start equipment automation. Internal automatic write state machine (WSM) Algorithms and timing required to perform block erase, program, and lock bits Configuration operation. The block erase operation erases one of the 128 KB blocks of the device, usually in one Second, it is independent of other blocks. Each block can be erased independently 100,000 Second evaluation. The block erase suspend mode allows the system software to suspend block erase to Read or program data from any other block. Similarly, program suspension allows the system Pause the programming software (byte/word programming and write buffer operations) Read data or execute code from any other unsuspended block. Each device contains a 256 bytes (x8 mode) or 256 words (x16 Mode) to achieve the best programming performance. By using the write buffer data is Program more efficiently in buffer increments. You can selectively lock memory blocks individually in the system. Personal block The lock uses the block lock bit to lock and unlock the block. Block lock bit gate block erase And the program runs. The lock bit configuration operation sets and clears the lock bit (use Set block lock bit and clear block lock bit commands).

4. Package overview