JS28F640P33TF70A

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1. Description

This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power-up or return from reset, the device defaults to asynchronous pagemode read. Configuring the RCR enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. The device features a 256-word buffer to enable optimum programming performance, which can improve system programming throughput time significantly to 1.8MByte/s. The P33-65nm SBC device supports read operations with VCC at 3.0V, and erase and program operations with VPP at 3.0V or 9.0V. Buffered Enhanced Factory Programming provides the fastest flash array programming performance with VPP at 9.0V, which increases factory throughput. With VPP at 3.0V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP ≤ VPPLK. The Command User Interface is the interface between the system processor and all internal operations of the device. An internal Write State Machine automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (16 bits). The one-time-programmable (OTP) Register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. The P33-65nm SBC device adds enhanced protection via Password Access Mode which allows user to protect write and/or read access to the defined blocks. In addition, the P33-65nm SBC device could also provide the full-device OTP permanent lock feature.

2. Features

    1. High performance

        - 60ns initial access time for Easy BGA

        - 70ns initial access time for TSOP

        - 25ns 8-word asynchronous-page read mode

        - 52MHz with zero wait states, 17ns clock-todata output synchronous-burst read mode

        - 4-, 8-, 16-, and continuous-word options for burst mode

        - 3.0V buffered programming at 1.8MByte/s (Typ) using 256-word buffer

        - Buffered Enhanced Factory Programming at 3.2MByte/s (typ) using 256-word buffer

    2. Architecture

        - Asymmetrically-blocked architecture

        - Four 32-KByte parameter blocks: top or bottom configuration

        - 128-KByte main blocks

        - Blank Check to verify an erased block

    3. Voltage and Power

        - VCC (core) voltage: 2.3V – 3.6V

        - VCCQ (I/O) voltage: 2.3V – 3.6V

        - Standby current: 35μA(Typ) for 64-Mbit, 50μA(Typ) for 128-Mbit

        - Continuous synchronous read current: 23mA (Typ) at 52 MHz

    4. Security

        - One-Time Programmable Registers

        - Absolute write protection: VPP = VSS

        - Power-transition erase/program lockout

        - Individual zero-latency block locking

        - Individual block lock-down capability

        - Password Access feature

    5. Software

        - 20µs (Typ) program suspend

        - 20µs (Typ) erase suspend

        - Basic Command Set and Extended Function Interface (EFI) Command Set compatible

        - Common Flash Interface capable

    6. Density and Packaging

        - 56-Lead TSOP package (128-Mbit, 64-Mbit)

        - 64-Ball Easy BGA package (128-Mbit, 64-Mbit)

        - 16-bit wide data bus

    7. Quality and Reliability

        - JESD47E Compliant

        - Operating temperature: –40°C to +85°C

        - Minimum 100,000 erase cycles per block

        - 65nm process technology