AS6C2016-55BINTR

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AS6C2016-55BINTR is a type of non-volatile Static Random Access Memory (nvSRAM) manufactured by Alliance Memory. Building upon the existing Power Nap technology, Alliance Memory’s Super SRAM™ offers the low power benefits of a memory technology so advanced, it eliminates the need for an external configuration register. Additionally, compared to earlier generations of nvSRAMs, Super SRAM enjoys a wide variety of new features such as an enhanced operating temperature range, advanced sleep modes, and superior reliability.

Standard AS6C2016-55BINTR nvSRAMs are offered with a wide operating voltage of 1.7V to 3.6V, with a maximum operating frequency of 40MHz. Other features include an extended temperature range from -40°C to +85°C, a low supply current of 450µA (typical), a write current of 5mA, a maximum 2°C/year data retention degradation rate, and up to 10 years of data retention.

The traditional technology used in nvSRAMs is masked programming or laser programming. This technology requires significant overhead in terms of lead time, cost, and memory reset times. In contrast, Super SRAM uses a speed-optimized, production-line mask set programming technique, allowing the device to retain configuration and control settings. As such, requiring no external logic or configuration registers, this unique feature also eliminates soft errors from portability and discretes.

The superior performance of Super SRAM is associated with several key design features. Analogous to an SRAM, Super SRAM requires a /WE signal for programming. A tech bit is pre-programmed with a unique signature that can be verified externally. In addition, a built-in logic block on the chip includes programmable bits for control circuit resetting if needed, as well as a variety of sleep modes for extremely low power consumption during inactive periods.

One of the most important features of this device is the high amount of storage options, which can be expanded up to 1MByte. This makes it suitable for applications that require long memories, such as embedded systems, Internet of Things (IoT) applications, industrial, healthcare, and many more. Additionally, two-level write protection, a hardware-based write enable signal, and on-chip write safety detection further enhance the security of data stored in the chip.

The working principle of the device is very simple. Upon receiving a HIGH level at the /WE signal, the device enters the program mode. All bytes of the memory can be programmed using a 16-bit data bus in the program mode. When the data are written, the /WE signal has to be driven LOW again in order to terminate the programming mode, allowing the device to enter data retention mode. Once the device enters the data retention mode, the internal writes enable lines are disabled, thus protecting the data.

In summary, Alliance Memory’s Ultra SRAM™ has several advantages over other nvSRAMs, including a wide operating voltage, low power consumption, a high storage capacity, and improved security. All of these features make it ideal for embedded systems, IoT applications, and other areas requiring long-term data storage.

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