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Memory field and Applications

NAND16GW3D2BN6E Engineering specifics

NAND16GW3D2BN6E is an embedded Multi-Chip Package (eMCP) NAND Flash memory device built on Toshiba’s proprietary BiCS 4 . It consists of sixteen 64Gb NAND Flash, an easy access-out integrated advanced interface and a flash controller. The NAND16GW3D2BN6E is designed for high-end mobile application with the highest memory capacity and performance.

Applications

NAND16GW3D2BN6E is widely used in applications such as mobile devices and digital cameras. As mobile device NAND capacity continues to expand, applications require higher density and more cost-effective solutions. The NAND16GW3D2BN6E is the ideal solution for expanding NAND flash memory capacity in mobile devices. This device is also ideal for other digital imaging appliances such as digital cameras due to its impressive performance, capacity, and RAM support.

Working Principle

NAND16GW3D2BN6E uses the Serial Peripheral Interface (SPI) protocol to communicate with the device. The SPI is a synchronous serial data transfer protocol which allows a master device (e.g., a microcontroller or microprocessor) to communicate with a slave device (e.g., the NAND Flash device) effectively over short distances. The SPI operates in full-duplex mode, meaning that it can both transmit and receive data simultaneously. The protocol requires a minimum of four wires for communication: a clock, a chip select, a data out, and a data in.

The BIOS/firmware of the device is responsible for controlling the data flow and the timing of the commands. The device may include multiple connections that allow data to be read and written simultaneously. This is possible via the different signals that are sent between the host and the NAND flash memory device. After power is provided, the device will begin to receive commands and data. The data is written to the NAND array in a series of steps using the controller hardware. Data is read from the NAND array using the same hardware.

The controller also handles Target Address Decode (TAD) when read/write commands are sent from the host to the NAND device. It also supports ECC (Error Correction Codes) to ensure data integrity. The controller also keeps track of the available blocks for write operations. The write operation is accomplished by erasing (or resetting) the information in an individual block of NAND memory and then writing the new information to the block. The read operation is accomplished by simply reading the contents of the requested block.

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