SI6924AEDQ-T1-E3

Vgs(th) (Max) @ Id:	1.5V @ 250µA
Base Part Number:	SI6924
Supplier Device Package:	8-TSSOP
Package / Case:	8-TSSOP (0.173", 4.40mm Width)
Mounting Type:	Surface Mount
Operating Temperature:	-55°C ~ 150°C (TJ)
Power - Max:	1W
Input Capacitance (Ciss) (Max) @ Vds:	--
Gate Charge (Qg) (Max) @ Vgs:	10nC @ 4.5V
Series:	--
Rds On (Max) @ Id, Vgs:	33 mOhm @ 4.6A, 4.5V
Current - Continuous Drain (Id) @ 25°C:	4.1A
Drain to Source Voltage (Vdss):	28V
FET Feature:	Logic Level Gate
FET Type:	2 N-Channel (Dual) Common Drain
Part Status:	Obsolete
Packaging:	Tape & Reel (TR)

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Introduction:

SI6924AEDQ-T1-E3 is a type of non-volatile, dual-channel, complementary FET array designed for switching applications in modern, low-power applications, such as handheld devices, telecommunication equipment and consumer electronics. They have a wide range of applications ranging from switching, power management, low-power audio amplification, to radio frequency modulation and demodulation. Using the latest CMOS technology, the device has two independent 8-bit registers that allow interfacing between logic and other circuits.

Construction:

The SI6924AEDQ-T1-E3 is composed of two cascode voltage switch (CVSW) stage gates and four insulated gate bipolar transistors (IGBTs). There are two gates for each IGBT which are connected to separate pins, allowing for logic-level control of the transistors. The gates can be connected to separate logic signals, resulting in two independent FET output stages. The device has an input voltage range of 5 to 24V and a thermal resistance of 0.15°C/W.

Operation:

The FET array works in tandem with an input control signal to control the current flow through the FET channel. When the control signal is LOW, the gates are turned OFF, resulting in a current-carrying FET channel. When the control signal is HIGH, the gates are turned ON, providing a high resistance that results in no current flow through the channel. This allows for simple switching applications.The device also features an integrated pull-down circuit for turning OFF both FET output stages. This means that when the control signal is LOW, both FETs are turned OFF simultaneously preventing any current from flowing through the device.

Advantages:

The SI6924AEDQ-T1-E3 is ideal for high-density low-power applications. It is incredibly compact due to its dual-channel, complement FET array construction. The device also has good thermal resistance and a long-term stability of 0.05%. Furthermore, the integrated pull-down circuit provides a fast switching speed and easy control of the output stages. The device also features low-noise capacitance, high-yield and low-cost, making it ideal for a wide range of applications such as switching and power management.

Conclusion:

The SI6924AEDQ-T1-E3 is an excellent choice for modern, low-power applications. It offers a wide range of features for switching and power management including its dual 8-bit registers for interfacing with logic, long-term stability, low thermal resistance, and its integrated pull-down circuit. With its small size and low cost, the device makes an ideal choice for modern, low-power applications.

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